[PDF.49np] CAPACITIVELY COUPLED CHIP-TO-CHIP INTERCONNECT DESIGN: A low-power high-bandwidth I/O solution for future high performance VLSI chips

CAPACITIVELY COUPLED CHIP-TO-CHIP INTERCONNECT DESIGN: A low-power high-bandwidth I/O solution for future high performance VLSI chips

[PDF.cl11] CAPACITIVELY COUPLED CHIP-TO-CHIP INTERCONNECT DESIGN: A low-power high-bandwidth I/O solution for future high performance VLSI chips

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 |  2010-05-06 | Original language:English | PDF # 1 |  8.66 x.32 x5.91l,.47 | File type: PDF | 140 pages

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I/O bandwidth in the Multi-Tb/s range is required for current and future high performance VLSI chips. This trend demands high-speed, high-density and low power I/Os. AC coupled interconnect (ACCI) has been demonstrated as a systematic solution for providing higher pin density and lower power dissipation. ACCI utilizes non-contact capacitor plates as signal I/O which yields a much higher pin density than traditional solder bump I/O. ACCI saves significant power with pulse...

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