[PDF.10pl] CMOS VLSI LOW-POWER DESIGN: DESIGN METHODOLOGY AND IMPLEMENTATION OF LOW-POWER ASYNCHRONOUS VITERBI DECODERS FOR WIRELESS APPLICATIONS

CMOS VLSI LOW-POWER DESIGN: DESIGN METHODOLOGY AND IMPLEMENTATION OF LOW-POWER ASYNCHRONOUS VITERBI DECODERS FOR WIRELESS APPLICATIONS

[PDF.og32] CMOS VLSI LOW-POWER DESIGN: DESIGN METHODOLOGY AND IMPLEMENTATION OF LOW-POWER ASYNCHRONOUS VITERBI DECODERS FOR WIRELESS APPLICATIONS

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 | #15700210 in Books |  2009-05-31 | Original language:English | PDF # 1 |  8.66 x.28 x5.91l,.41 | File type: PDF | 120 pages

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||About the Author|Dr. Mohamed Kawokgy is a senior design engineer at Intel Corporation. He received his B.Sc. degree at University of Alexandria, Egypt, in 2001. He received his M.A.Sc. and Ph.D. degrees, in VLSI design, at University of Toronto, Canada, in 2

Power dissipation is a critical parameter in digital design for the implementation of high performance portable, battery operated systems, such as wireless communications systems. Clocked or synchronous digital designs consume a significant amount of power associated with coordinating the operation of millions of transistors at GHz clock rates. Besides, the operating speed of such systems is limited by the slowest functional logic unit. By contrast, asynchronous...

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