[PDF.23ho] Manufacturability Aware Routing in Nanometer VLSI (Foundations and Trends(r) in Electronic Design Automation)
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Manufacturability Aware Routing in Nanometer VLSI (Foundations and Trends(r) in Electronic Design Automation)
David Z. Pan, Minsik Cho, Yuan
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| 2010-04-15 | Original language:English | PDF # 1 | 9.21 x.23 x6.14l,.37 | File type: PDF | 112 pages|
Nanometer very large scale integrated (VLSI) circuit design faces tremendous challenges due to the manufacturing limitations. These manufacturing and process related challenges include the printability issues due to deep sub-wavelength lithography, the topography variations due to chemical-mechanical polishing (CMP), the random defects due to missing or extra material, and so on. Thus, design "closure" may not automatically guarantee the manufacturing closure due to the ...
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