[PDF.15px] Power-Constrained Testing of VLSI Circuits: A Guide to the IEEE 1149.4 Test Standard (Frontiers in Electronic Testing)

Power-Constrained Testing of VLSI Circuits: A Guide to the IEEE 1149.4 Test Standard (Frontiers in Electronic Testing)

[PDF.mr69] Power-Constrained Testing of VLSI Circuits: A Guide to the IEEE 1149.4 Test Standard (Frontiers in Electronic Testing)

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 |  Nicolici Nicola Al Hashimi Bashir M |  2010-12-09 |  2013-10-04 | Original language:English | PDF # 1 |  9.25 x.44 x6.10l,.61 | File type: PDF | 178 pages

 | Power Constrained Testing of VLSI Circuits

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This text focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the VLSI design flow. It surveys existing techniques and presents several test automation techniques for reducing power in scan-based sequential circuits and BIST data paths.

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