[PDF.01zv] Strategies to Reduce Power during VLSI Circuit Testing: Reduction of Dynamic and Leakage Power during Testing of Digital VLSI Circuits
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Strategies to Reduce Power during VLSI Circuit Testing: Reduction of Dynamic and Leakage Power during Testing of Digital VLSI Circuits
Subhadip Kundu, Santanu Chattopadhyay
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| 2012-09-25 | 2012-09-25 | Original language:English | 8.66 x.27 x5.91l, | File type: PDF | 116 pages||About the Author|Mr. Subhadip Kundu received his B.Tech degree from WBUT in 2007 and MS degree from IIT Kharagpur in 2010. Currently, He is pursuing PhD in Department of CSE, IIT Kharagpur. His current areas of research are: Fault diagnosis, Thermal and Power aw
Testing is now considered as one of the most important issues in the development process of integrated circuits. With the advent of deep sub-micron (DSM) technology, the tight constraints on power dissipation have created new challenges for testing low power VLSI circuits. This necessitates redesigning the traditional test techniques that do not account for power dissipation during test application. Test power is always expected to be higher than that in the normal mode ...
You can specify the type of files you want, for your device.Strategies to Reduce Power during VLSI Circuit Testing: Reduction of Dynamic and Leakage Power during Testing of Digital VLSI Circuits | Subhadip Kundu, Santanu Chattopadhyay. I was recommended this book by a dear friend of mine.
