[PDF.37nu] Test Vector Reordering Method for Low Power Testing: Test Vector Reordering Method for Minimizing Power Dissipation in VLSI Circuits using Functional Metrics

Test Vector Reordering Method for Low Power Testing: Test Vector Reordering Method for Minimizing Power Dissipation in VLSI Circuits using Functional Metrics

[PDF.qi96] Test Vector Reordering Method for Low Power Testing: Test Vector Reordering Method for Minimizing Power Dissipation in VLSI Circuits using Functional Metrics

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 |  2012-07-18 | Original language:English | PDF # 1 |  8.66 x.18 x5.91l,.27 | File type: PDF | 76 pages

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||About the Author|Dr.K.Paramasivam got UG & PG engineering degree in 1995 & 97 from Bharathiar University. He got PhD(Low power VLSI Testing) at Anna University Chennai in 2009. Presently he is with Bannari Amman Institute of Technology, TN, India. He has 16 & 10

The book investigates test vector reordering algorithm for minimizing the power dissipation during testing of VLSI circuits. Testing plays a key role in design flow and is the major challenging task for design and test engineers. Power dissipation is critical problem during testing phase. The test vectors generated from Automatic Test Pattern Generator used for testing are statistically independent which leads to more power dissipation. The testing power can be reduced b...

You easily download any file type for your device.Test Vector Reordering Method for Low Power Testing: Test Vector Reordering Method for Minimizing Power Dissipation in VLSI Circuits using Functional Metrics   |  K. Paramasivam, K. Gunavathi. Which are the reasons I like to read books. Great story by a great author.

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