[PDF.29ci] Timing and Signal Integrity Issues with VLSI Interconnects: In sub-nanometer designs

Timing and Signal Integrity Issues with VLSI Interconnects: In sub-nanometer designs

[PDF.uz63] Timing and Signal Integrity Issues with VLSI Interconnects: In sub-nanometer designs

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 | #14276457 in Books |  2011-11-09 | Original language:English |  8.66 x.19 x5.91l, | File type: PDF | 84 pages

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||About the Author|Debaprasad Das is Assistant Professor, Department of Electronics and Communication Engineering, Meghnad Saha Institute of Technology, Kolkata, India. He was a Senior Engineer at the ASIC product development centre, Texas Instruments, Bangalore,

This book discusses the timing and signal integrity issues with VLSI interconnects in sub-nanometer designs. Starting with the basics of interconnect equivalent circuit model it describes the RLC equivalent models of interconnects, their extraction methodologies, and circuit simulation for timing and signal integrity analysis. With enormous analysis results for different technology nodes the importance of on-chip inductive effects has been discussed. The sample simu...

You can specify the type of files you want, for your device.Timing and Signal Integrity Issues with VLSI Interconnects: In sub-nanometer designs   |  Debaprasad Das. A good, fresh read, highly recommended.

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